The present invention relates to the structure of a semiconductor device, and more particularly to high-density lateral bipolar transistors having the performances of high operating speed and low power dissipation.
FIG. 1 shows a sectional structural view of a prior-art lateral p-n-p transistor. An impurity is diffused selectively into the surface of a p-type substrate 11, to form an n.sup.+ -type buried layer 14. Thereafter, an n-type epitaxial layer 15 is grown and is doped with boron from its surface so as to form p-type regions 12 and 13. Further, it is doped with phosphorus to form an n.sup.+ -type layer 16. The portion 12 is used as an emitter layer, the portion 15 as a base layer, and the portion 13 as a collector layer. The diffused layers 14 and 16 are used as a low resistivity layer for leading out the base region to an electrode 17B. In the figure, symbol 17E denotes an emitter electrode, symbol 17C a collector electrode, symbol 17B the base electrode, and numeral 10 an insulator. The prior-art p-n-p transistor shown in FIG. 1 is extensively employed owing to a simple fabrication process, but it has disadvantages to be mentioned below:
(1) In a transistor action, holes injected from an emitter to a base should preferably be all collected to a collector. With the structure shown in FIG. 1, however, most of holes injected from the bottom part of the emitter diffused layer 12 flow out to the base electrode 17B through the diffused layer 14. In consequence, the power dissipation increases, and the current gain decreases.
(2) The emitter electrode 17E and collector electrode 17C must be taken out from holes (contact holes) which are smaller than the emitter diffused region 12 and collector diffused region 13, respectively. Therefore, the emitter and collector diffused regions become at least larger than the contact holes. The size of the contact holes is determined by lithography, and it is difficult to be rendered small. More specifically, the size of the contact holes is reduced to the utmost. Accordingly, the regions of the diffused layers 12 and 13 infallibly become larger than the smallest possible size of the contact holes. Consequently, the emitter-base junction capacitance and the collector-base junction capacitance increase in proportion to the resulting larger junction areas, to worsen the high frequency characteristics of the transistor.
(3) The switching speed of a transistor is determined by the charges of electrons and hole which are stored within the transistor. Holes stored underneath the emitter layer 12 and collector layer 13 degrade the operating speed of the transistor drastically.
FIG. 2 shows a plan view of another prior-art lateral p-n-p transistor devised in order to eliminate the above disadvantages, while FIG. 3 shows a structural sectional view taken along II--II' in FIG. 2. An impurity is diffused into the surface of a p-type substrate 11, thereby to form an n.sup.+ -type region 14. The whole surface is thereafter oxidized to form a thermal oxide film 22. After selectively etching parts of the oxide film 22, an epitaxial layer is grown on the whole surface. A single crystal layer 15 is grown on a part 20 at which the substrate is exposed, while a polycrystalline silicon layer 21 (21E, 21C) is grown on the insulator 22. Using a mask, regions 21E, 21C, 12 and 13 are selectively doped with boron, to form the emitter diffused region 12 and the collector diffused region 13. The unnecessary part of the polycrystalline silicon not to be used for the transistor is selectively removed by employing a mask. Thus, the lateral p-n-p transistor in FIGS. 2 and 3 is formed. In this example, the portion 21E underneath an emitter electrode 17E and the portion 21C underneath a collector electrode 17C are electrically insulated from the substrate 11 or diffused layer 14 by the silicon oxide film 22, so that the emitter-base junction capacitance and the collector-base junction capacitance decrease.
Further, carriers to be stored decrease.
Accordingly, the lateral p-n-p transistor of low power dissipation and high operating speed is realized. Such an example is disclosed in Japanese Patent Application Publication No. 53-23669, and an example of a vertical bipolar transistor is disclosed in U. S. Pat. No. 3,600,651. Even with the technique, however, the following disadvantages are involved:
(I) When current to flow through a transistor has been determined, the voltage difference V.sub.BE between the base and emitter thereof is determined by a base length L. This base length L is determined by the etching of a polycrystalline silicon layer. More specifically, the emitter-base junction is determined by the interface between the region 12 and the region 15, and the collector-base junction by the interface between the region 13 and the region 15. They are proportional to the etching width L of the polycrystalline silicon layer. The polycrystalline silicon layer is as thick as about 1 .mu.m, and is liable to a non-uniform etching rate on account of an inferior crystallinity. Since the controllability of the etching is inferior, the base length L must be rendered sufficiently great in order to fabricate a transistor of stable characteristics. In consequence, the occupation area of the element becomes large.
(II) A large number of crystal defects arise at the interface between the single crystal layer 15 and the polycrystalline layer 21, and it is unfavorable for transistor characteristics to use the interface as the base region of the transistor. For this reason, the emitter and collector diffused layers 12 and 13 need to be formed sufficiently internally of the opening 20 of the oxide film. Therefore, it is difficult to make the opening 20 small, and the occupation area of the element enlarges.
(III) The opening 20 of the oxide film 22 must lie inside the polycrystalline silicon layer 21. This is intended to prevent the substrate region 14 in the opening 20 from being etched by the etching step for the polycrystalline silicon layer 21. On account of such arrangement, a part 23 of the base region (FIG. 2) has a very poor crystallinity. Therefore, a leakage current arises through crystal defects. For this reason, the controllability of the collector current is inferior, and the transistor has characteristics which can be hardly employed in practical use. To the end of avoiding the drawback, such an improvement as etching and removing the region 23 or turning it into a silicon oxide film by a thermal step is considered. However, it makes the formation of a small-sized transistor difficult.